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74LS138 1 of 8 Decoder De Multiplexer

  • Designed specifically for high speed:
    • Memory decoders
    • Data transmission systems
  • DM74LS138 3-to-8-line decoders incorporates 3 enable inputs to simplify cascading and/or data reception
  • Schottky clamped for high performance
The DM74LS138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

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